The present invention relates generally to a method of manufacturing a semiconductor memory device having trench capacitors. More particularly, the invention is concerned with a method of manufacturing a semiconductor memory device which includes trench capacitors and which is profitably suited for use as a dynamic random access memory or DRAM in abbreviation.
Heretofore, the DRAM in which stacked trench capacitors are employed has been manufactured by a method shown in FIGS. 9 to 11 of the accompanying drawings, as is disclosed, for example, in "Process Interaction for 64M DRAM using An Asymmetrical Stacked Trench Capacitor (AST) Cell" IEDM 90, pp. 647-650, "A 4.2 .mu.m.sup.2 Half-Vcc Sheath-Plate Capacitor DRAM Cell with Self-Aligned Buried Plate-Wiring" IEDM, pp. 232-335, and "Denshi Zairyo", (Electronic Material) June 1991, pp. 37-43.
This prior art manufacturing method will first be described. Referring to FIG. 10 of the accompanying drawings, there is first formed over a surface of a monocrystalline silicon substrate 101 an element isolating insulation film 102 by a LOCOS (Local Oxidation Of Silicon) method. Thereafter, a trench 103 is formed in the silicon substrate 101, for example, by a RIE Reactive Ion Etching) method. Subsequently, an insulation film 104 is formed over the whole surface of the silicon substrate 101 inclusive of inner wall surfaces of the trench 103 by a thermal oxidation method or a CVD (Chemical Vapor Deposition) method. This insulation film 104 serves for electrically isolating from the silicon substrate 101 the capacitor electrode which is formed within the trench 103 later on and serves at the same time for preventing occurrence of current leakage between the adjacent trenches, a so-called soft error and the like.
Subsequently, the trench 103 is filled or buried with a resist material or silicon 105 to an intermediate level in depth, whereupon a resist layer 106 is deposited in such a pattern that only a part of the opening of the trench 103 is exposed, as is illustrated in FIG. 11. By using the resist or silicon layer 105 and the resist layer 106 as a mask, a portion of the insulating film 104 is removed by etching to thereby expose a contact area 107 to be used for contacting a storage node of a capacitor and the silicon substrate 101 to each other.
Next, referring to FIG. 9, after removal of the resist layer 106 and the resist or silicon layer 105 (or at least a part thereof), a storage node 108, a capacitor insulation film 109 and a cell plate 110 are formed successively within the trench 103 to thereby realize a stacked trench capacitor. Subsequently, a gate oxidation film 112 is formed on the silicon substrate 101, for example, by a thermal oxidation method and then a diffused layer 111 is formed in the silicon substrate 101 for realizing contact with the storage node 108 of the stacked trench capacitor.
In succession, there are formed a gate electrode 113, diffused layers 114 serving as source and drain regions of a transistor, an inter-layer insulation film 115 and a diffused layer 116 for making contact with a bit line, respectively. Additionally, wiring conductors 119 for the bit line 117, an inter-layer insulation film 118 and a gate electrode 113, respectively, are formed. Finally, a passivation film 120 is formed over the whole surface.
As is apparent from the above description, the prior art semiconductor memory manufacturing method is disadvantageous in that the process is very complicated because there are required two layers of the etching masks 105 and 106 for forming the contact area 107 and additionally the patterning process for patterning the resist layer 106.
Further, difficulty is encountered in patterning the resist layer 106 in a desired shape with a satisfactory accuracy because of possibility of misalignment of an illumination unit and/or insufficient exposure due to presence of offset in the substrate, as a result of which it has been very difficult to realize the contact area 107, involving eventually difficulty in manufacturing the DRAM as a whole with a stable yield. Besides, because a margin is required for the mask alignment upon patterning of the resist layer 106, the hitherto known method is not suited for the manufacture of the DRAM of high integration and high density.
Additionally, it is noted that in the case of the known manufacturing method described above, the trench 103 is formed after deposition of the element isolating insulation film 102 through the LOCOS method. Consequently, tolerance or margin must be taken into account in the design by considering the misalignment between the masks used in the various process steps and the illuminating unit and unevenness in the length of bird's-beak of the insulation film 102. For these reasons, implementation of the DRAM in high integration and high density has been difficult